DocumentCode :
1855965
Title :
Simulation and modeling of heat-dissipation packaging for nanoscale GaInP/GaAs collector-up HBTs
Author :
Chang, Jhin-Fong-Chin ; Tseng, Hsien-Cheng
Author_Institution :
Department of Electronic Engineering, Kun Shan University, 949, DaWan Road, Tainan 71003, Taiwan, R.O.C.
fYear :
2013
fDate :
26-28 Aug. 2013
Firstpage :
167
Lastpage :
169
Abstract :
A heat-dissipation packaging structure, with graphene plated-heat-sink (PHS) layer, of GaInP/GaAs collector-up HBTs has been designed and evaluated by finite-element modeling technique. Based on 2-D and 3-D systematic analyses, it is indicated that the reported configuration can be further minimized by 34%. Consequently, thinning the thermal via constructed underneath the GaInP/GaAs collector-up HBT should be effective for the shrinkage of heat-dissipation packaging configurations, and the proposed approach has been demonstrated to be useful for optimizing HBT-based amplifiers in future mobile communication systems.
Keywords :
HBT; collector-up; finite-element modeling; graphene; packaging;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ASQED), 2013 5th Asia Symposium on
Conference_Location :
Penang
Print_ISBN :
978-1-4799-1312-1
Type :
conf
DOI :
10.1109/ASQED.2013.6643581
Filename :
6643581
Link To Document :
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