DocumentCode :
1856026
Title :
Parallel design for parallel decision feedback decoders for 10GBASE-T
Author :
Gu, Yongru ; Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Minnesota Univ., USA
Volume :
2
fYear :
2004
fDate :
25-28 July 2004
Abstract :
10GBASE-T (10 Gigabit Ethernet over unshielded twisted pairs) will probably use a 10-level pulse amplitude modulation (PAM10) as well as a 4D trellis code as in 1000BASE-T (1000 Megabit Ethernet over copper medium). One of most powerful approaches to decode the code is called parallel decision-feedback decoding. However, VLSI implementation of a PDFD (parallel decision-feedback decoder) operating at 833 MHz is extremely challenging due to its long critical path. This paper extends the word-level parallel processing technique for Viterbi decoders to design high speed parallel PDFDs. Compared with the straight-forward implementation of PDFDs, a 2-level parallel PDFD can achieve a speedup of 1.5 while the speedup for a 3-level parallel PDFD is around 2. More speedup is achievable if we combine some other techniques, such as pre-computation technique.
Keywords :
Viterbi decoding; decision feedback equalisers; local area networks; parallel processing; pulse amplitude modulation; trellis codes; 1000BASE-T; 10GBASE-T; 4D trellis code; 833 MHz; Ethernet; VLSI implementation; Viterbi decoders; parallel decision feedback decoders; parallel design; pulse amplitude modulation; word-level parallel processing technique; Amplitude modulation; Convolutional codes; Copper; Decoding; Ethernet networks; Feedback; Parallel processing; Pulse modulation; Very large scale integration; Viterbi algorithm;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
Type :
conf
DOI :
10.1109/MWSCAS.2004.1354134
Filename :
1354134
Link To Document :
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