High speed VLSI architecture for bit plane encoder of JPEG2000

The bit plane coder is a part of the JPEG2000 embedded block coder. Its throughput plays a key role in deciding the overall throughput of a JPEG2000 encoder. In this paper we present a parallel pipeline VLSI architecture for the bit plane encoder which processes a complete stripe-column concurrently during every pass. The hardware requirements and the critical path delay of the proposed technique are compared with the existing solutions. The experimental results show that the proposed architecture has 2.6 times greater throughput than existing architectures, with a comparatively small increase in hardware cost.