An efficient line based VLSI architecture for 2D lifting DWT

This paper presents a line based VLSI architecture for real time processing of 2D lifting discrete wavelet transform (DWT). The architecture computes lifting operation based on state space representation and uses RPA (Recursive Pyramid Algorithm) scheme. To improve hardware utilization, the filter that is responsible for column operations of the first level performs both the row and column operations of the second and following levels. As a result, the architecture has the 66.7%-88.9% hardware utilization and requires only 9 multipliers and 12 adders for biorthogonal (9,7)/(5,3) filter, which is a smaller hardware complexity compared to that of other architecture with comparable throughput.