DocumentCode
1856609
Title
Wafer level packaging of micro/nanosystems
Author
Pieters, Philip
Author_Institution
IMEC, Leuven, Belgium
fYear
2005
fDate
11-15 July 2005
Firstpage
130
Abstract
Starting with the identification of the need to come to more cost-effective processing and packaging of micro/nanosystems, we present a number of wafer level packaging techniques that may enable this. Additionally, interconnectivity and reliability and failure analysis play an important role in improving performance, yield and in the end cost-effectiveness. Therefore a number of important analysis techniques are presented.
Keywords
failure analysis; micromechanical devices; nanotechnology; packaging; reliability; analysis techniques; cost-effective processing; failure analysis; interconnectivity; microsystems; nanosystems; reliability; wafer level packaging; Assembly systems; Costs; Encapsulation; Failure analysis; Nanoscale devices; Packaging; Protection; Radiofrequency microelectromechanical systems; Transistors; Wafer scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Nanotechnology, 2005. 5th IEEE Conference on
Print_ISBN
0-7803-9199-3
Type
conf
DOI
10.1109/NANO.2005.1500710
Filename
1500710
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