Online error detection in SRAM based FPGAs using Scalable Error Detection Coding

SRAM based devices are more susceptible to unidirectional errors when exposed to radiations. This paper presents an error detection scheme for detecting errors in SRAM cells of FPGA. This proposed Scalable Error Detection Coding (SEDC) scheme is capable of detecting 100% unidirectional errors. SEDC scheme partitions the data into segments of 2-, 3- and 4-bits data and encodes these segments using SEDC codes, in parallel fashion. The programming device generates the SEDC check bits and stores them on the FPGA´s SRAM cells. A high speed, compact and easily scalable online SEDC check bit generator generates the SEDC check bits, which are compared with the pre-stored check bits during circuit operation. All unidirectional errors in SRAM cells, caused by cosmic radiations, are detected. The proposed technique achieves significant improvement in area as well as speed over Berger & simple TMR technique for the same application.