Design and multiplier-less realization of matched filters with variable fractional delay for software radio receivers

This paper studies the design and multiplier-less realization of variable fractional delay matched filters (VFD-MFs), which provide matching filtering and variable fractional delay of the filter output. It offers greater flexibility and lower delay in symbol-timing adjustment than directly cascading a match filter with a fractional delayer. The design of VFD-MFs, which can be viewed as a variable digital filter (VDF) design problem subject to the matched filtering condition, is formulated as a second order cone programming (SOCP) problem with least square design criteria. The proposed VFD-MFs can be efficiently implemented using the Farrow structure. By employing sum-of-power-of-two (SOPOT) coefficients and the multiplier block (MB) technique, very efficient multiplier-less realization of the VFD-MF with low hardware complexity is obtained. A design example is given to demonstrate the effectiveness of the proposed approach.