A simulation-based approach to integrated performance and reliability modeling using VHDL

This paper presents a methodology which creates a single-path design environment based on a hardware description language (HDL). This methodology allows high-level performance and reliability modeling to be performed using the same HDL and simulation environment as used to perform detailed design. The approach is based on a set of building blocks which allows the system designer to describe the performance, functional, and reliability characteristics of the system in a very efficient and intuitive fashion. Simulatable-Failure-Modes-and-Effects-Analysis (SFMEA) is also supported. In fact, the significant advantage of the approach is that the same modeling language and environment can be used from conceptual design to implementation, thus avoiding the need to translate among different Computer-Aided Design (CAD) tools. The specific HDL employed is the VHSIC (Very High Speed Integrated Circuit) hardware description language (VHDL), which is an IEEE standard (IEEE 1076). The paper discusses the methodology under development and its application to the design and analysis of real-time, fault-tolerant systems