Adaptive analog timer for on-chip testing

Author

Provost, B. ; Sánchez-Sinencio, E.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1999

fDate

1999

Firstpage

29

Lastpage

32

Abstract

A practical approach for generating precise and slow analog ramps to be used for on-chip time-domain analog testing and for monotonicity and histogram test of ADCs is introduced. The calibration uses a discrete-time adaptive scheme. Two implementations of the approach are proposed; one is continuous-time and the second is discrete-time. Convergence criteria are defined. Results from a fabricated circuit in a low-cost 2 μm technology are in agreement with theoretical results

Keywords

analogue integrated circuits; analogue-digital conversion; calibration; continuous time systems; discrete time systems; integrated circuit testing; time-domain analysis; 2 micron; ADCs; calibration; continuous-time analysis; convergence criteria; discrete-time adaptive scheme; discrete-time analysis; histogram test; monotonicity; on-chip testing; time-domain analog testing; Analog-digital conversion; Bandwidth; Capacitors; Circuit testing; Delay; Frequency domain analysis; Histograms; Pulse measurements; System testing; Time domain analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on

Conference_Location

Puerto Vallarta

Print_ISBN

0-7803-5588-1

Type

conf

DOI

10.1109/MMICA.1999.833587

Filename

833587