Title :
Nanocore/CMOS hybrid system-on-package (SoP) architecture for autonomous error-tolerant (AET) cellular array network
Author :
Liu, Jian ; Weerasekera, Roshan ; Zheng, Li-Rong ; Tenhunen, Hannu
Author_Institution :
Lab. of Electron. & Comput. Syst., Microelectron. & Inf. Technol., Kista, Sweden
Abstract :
In this paper, the nanocore/CMOS hybrid system-on-package (SoP) autonomous error-tolerant (AET) cellular network architecture, which integrates today´s mature CMOS technology with emerging nanotechnology, is proposed. Within the cellular network, each AET cell contains a nanocore, CMOS cell peripherals and their interface circuits in a silicon platform. The overall network is homogeneous. These imply strict constraints for intercellular connection schemes and routing policies. Depending on the communication requirement between two nodes.
Keywords :
CMOS integrated circuits; cellular arrays; fault tolerance; nanoelectronics; system-in-package; Si; autonomous error-tolerant cellular array network; intercellular connection schemes; interface circuits; nanocore-CMOS hybrid system-on-package architecture; nanotechnology; silicon platform; CMOS technology; Cellular networks; Computer architecture; Computer errors; Electrons; Integrated circuit interconnections; Land mobile radio cellular systems; Nanoscale devices; Nanotechnology; Silicon;
Conference_Titel :
Nanotechnology, 2005. 5th IEEE Conference on
Print_ISBN :
0-7803-9199-3
DOI :
10.1109/NANO.2005.1500724
