• DocumentCode
    1857114
  • Title

    A Novel BIST Scheme Using Test Vectors Applied by Circuit-under-Test Itself

  • Author

    Kuang, Jishun ; Ouyang, Xiong ; You, Zhiqiang

  • Author_Institution
    Sch. of Comput. & Commun., Hunan Univ., Changsha
  • fYear
    2008
  • fDate
    24-27 Nov. 2008
  • Firstpage
    75
  • Lastpage
    80
  • Abstract
    A new built-in-self-test scheme, referred to as Test Vectors Applied by Circuit-under-Test (TVAC), is proposed in this paper. As the point of view of the paper, Circuit-under-Test (CUT) is no longer only regarded as a test object, but also a kind of available resources. By feedback connecting some of the CUTpsilas interior nodes to the input terminals, the method can generate a test set with low area overhead, short test application time, and enable at-speed testing. A ldquofeedback groupingrdquo search algorithm is presented for a given CUT and its test set. The experimental results on ISCAS85 benchmark circuits and MinTest test sets demonstrate that the proposed scheme not only can achieve almost 100% single stuck-at fault coverage, but also has an average 54.1% reduction in test pattern length compared with LFSR reseeding approaches, and an average 6.1% extra area overhead over the area of the largest five CUTs. The percentage of extra area overhead is not sensitive to the size of the CUT.
  • Keywords
    built-in self test; fault diagnosis; integrated circuit testing; logic testing; BIST scheme; circuit-under-test; integrated circuit testing; search algorithm; stuck-at fault; test vectors; Built-in self-test; Circuit faults; Circuit testing; Costs; Design for testability; Feedback; Logic testing; Read only memory; Registers; Software testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Test Symposium, 2008. ATS '08. 17th
  • Conference_Location
    Sapporo
  • ISSN
    1081-7735
  • Print_ISBN
    978-0-7695-3396-4
  • Type

    conf

  • DOI
    10.1109/ATS.2008.25
  • Filename
    4711562