Title :
Implementing proper ASIC design margins: a must for reliable operation
Author :
Willing, Walter E. ; Helland, Arden R.
Author_Institution :
Westinghouse Electr. Corp., Baltimore, MD, USA
Abstract :
This paper presents some of the basic timing related design parameters for digital ASICs (propagation delay, operating frequency) where sufficient margin must exist to preclude operational failures caused by performance degradation from such effects as: aging, nuclear radiation, voltage, temperature and variability in processing. As ASICs and gate arrays become the standard building blocks for digital circuits and systems, reliability engineers must be aware of these parameters and methods for assuring proper design margin. The techniques utilized on a high reliability program to define and quantify the timing for their ASIC designs will be presented to illustrate these concepts. Although the specific examples shown are for CMOS/SOS devices, applying these or similar techniques can provide an optimization between ASIC performance and long term operational reliability for any ASIC technology
Keywords :
CMOS integrated circuits; application specific integrated circuits; circuit CAD; circuit reliability; integrated logic circuits; logic CAD; logic arrays; ASIC design margins; CMOS devices; SOS devices; aging; digital ASICs; gate arrays; nuclear radiation; operating frequency; operational failure prevention; performance degradation; propagation delay; reliability engineers; temperature; variability; voltage; Aging; Application specific integrated circuits; Degradation; Digital circuits; Frequency; Propagation delay; Reliability engineering; Temperature; Timing; Voltage;
Conference_Titel :
Reliability and Maintainability Symposium, 1994. Proceedings., Annual
Conference_Location :
Anaheim, CA
Print_ISBN :
0-7803-1786-6
DOI :
10.1109/RAMS.1994.291157