Title :
A clock and data recovery IC for communications and radar applications
Author :
Capofreddi, Peter D. ; Baringer, Cynthia D. ; Jensen, Joseph E. ; Rodwell, Mark J.W. ; Posey, William P. ; Yung, Michael W. ; Xie, Yi-Ming
Author_Institution :
LLC, HRL Labs., Malibu, CA, USA
Abstract :
A clock and data recovery (CDR) circuit for communications and radar applications was designed and fabricated in a 0.8 μm, 27 GHz f T bipolar process. Experimental measurements demonstrate that the circuit achieves a data rate of 4 Gbit/s with a bit error rate less than 10-7. The circuit includes two phase-locked loops for clock recovery, a delay-locked loop for synchronizing multiple channels with different path delays, and a 1:16 tree-type demultiplexer. In operation, the circuit consumes 3 W from a single 3.3 V power supply
Keywords :
bipolar integrated circuits; delay lock loops; demultiplexing equipment; error statistics; mixed analogue-digital integrated circuits; phase locked loops; radar equipment; synchronisation; telecommunication equipment; 0.8 micron; 27 GHz; 3 W; 3.3 V; 4 Gbit/s; ASIC; BER; bit error rate; clock recovery IC; communications applications; data recovery IC; delay-locked loop; multiple channels; path delays; phase-locked loops; radar applications; submicron bipolar process; tree-type demultiplexer; Application specific integrated circuits; Clocks; Delay; Inductance; Logic testing; Phase locked loops; Radar applications; Signal processing; Voltage; Voltage-controlled oscillators;
Conference_Titel :
Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on
Conference_Location :
Puerto Vallarta
Print_ISBN :
0-7803-5588-1
DOI :
10.1109/MMICA.1999.833604
