High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology

Author

Giles, M.D. ; Arkali Radhakrishna, N. ; Becher, D. ; Kornfeld, A. ; Maurice, K. ; Mudanai, S. ; Natarajan, S. ; Newman, P. ; Packan, P. ; Rakshit, T.

Author_Institution

Design Technol. Solutions, Intel Corp., Hillsboro, OR, USA

fYear

2015

fDate

16-18 June 2015

Abstract

Random variation of threshold voltage (Vt) in MOSFETs plays a central role in determining the minimum operating voltage of products in a given process technology. Properly characterizing Vt variation requires a large volume of measurements of minimum size devices to understand the high sigma behavior. At the same time, a rapid measurement approach is required to keep the total measurement time practical. Here we describe a new test structure and measurement approach that enables practical characterization of Vt distributions to high sigma and its application to 14nm Logic FinFET technology. We show that both NMOS and PMOS single fin devices have very low random Vt variation of 19mV and 24mV respectively, normally distributed out to +/-5σ.

Keywords

MOSFET; logic circuits; semiconductor device measurement; semiconductor device testing; voltage measurement; MOSFET; NMOS; PMOS; high sigma measurement; logic FinFET technology; random threshold voltage variation; rapid measurement approach; single fin devices; size 14 nm; voltage 19 mV; voltage 24 mV; FinFETs; Logic gates; Periodic structures; Threshold voltage; Time measurement; AVt; FinFET; threshold voltage; variation;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI Technology), 2015 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2015.7223657

Filename

7223657