DocumentCode
1857424
Title
A dynamic dither ΣΔ ADC with 103 dB DR for audio applications
Author
Gomez, Gabriel J.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
1999
fDate
1999
Firstpage
130
Lastpage
133
Abstract
A sigma-delta Analog to Digital Converter (ADC) using dynamic dither to achieve a tone-free Dynamic Range (DR) of 103 dB in an audio bandwidth is presented. The design was implemented using a 3rd order 2-1 cascade architecture with an oversampling ratio of 128. The ADC modulator consumes 22 mW from a 3.0 V power supply and was fabricated in 0.6 μm CMOS (analog portion) and 0.3 μm CMOS (digital portion) using Multi-Chip-Module (MCM) technology
Keywords
CMOS integrated circuits; audio signal processing; multichip modules; sigma-delta modulation; 0.3 micron; 0.6 micron; 22 mW; 3 V; 3rd order 2-1 cascade architecture; CMOS chips; MCM technology; analog to digital converter; audio applications; dynamic dither ΣΔ ADC; oversampling ratio; sigma-delta modulator; tone-free dynamic range; Band pass filters; CMOS process; CMOS technology; Capacitors; Codecs; Digital filters; Digital modulation; Error correction; Finite impulse response filter; Sampling methods;
fLanguage
English
Publisher
ieee
Conference_Titel
Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on
Conference_Location
Puerto Vallarta
Print_ISBN
0-7803-5588-1
Type
conf
DOI
10.1109/MMICA.1999.833616
Filename
833616
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