Real-time integer convolution implemented using systolic arrays and a digit-serial architecture in complex programmable logic devices

Author

Santillan Q., G.F. ; Iparraguirre C., D.

Author_Institution

Electr. & Electron. Section, Pontificia Univ. Catolica del Peru

fYear

1999

fDate

1999

Firstpage

147

Lastpage

150

Abstract

In this work an FIR filter is designed, combining the systolic architecture with the digit-serial technique. Multipliers are designed with this technique and the accumulator exploits these characteristics avoiding the lack of real-time computing capability and data processing speed. The system can be used in realtime digital signal and image processing applications. The simulation results presented were obtained using the FLEX 10K20 device of Altera

Keywords

FIR filters; convolution; real-time systems; systolic arrays; Altera; FIR filter; FLEX 10K20 device; complex programmable logic devices; data processing speed; digit-serial architecture; digit-serial technique; image processing applications; real-time computing capability; real-time integer convolution; systolic arrays; Clocks; Computer architecture; Convolution; Data processing; Image processing; Parallel processing; Pipeline processing; Real time systems; Signal processing; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on

Conference_Location

Puerto Vallarta

Print_ISBN

0-7803-5588-1

Type

conf

DOI

10.1109/MMICA.1999.833620

Filename

833620