A high-performance convolver systolic array

Author

Hernández, Mariano Aguirre ; Aranda, Mónico Linares

Author_Institution

Inst. Nacional de Astrofisica, Opt. y Electron., Puebla, Mexico

fYear

1999

fDate

1999

Firstpage

151

Lastpage

154

Abstract

Convolution is a very important and useful operation in the field of digital signal processing. In this paper, the design of a high performance CMOS convolver circuit of digital signals, is presented. The circuit was designed with a bit-level systolic array architecture with unidirectional data flow. In order to allow high-speed operation, a dynamic logic style of true single-phase clock was used and some low-power techniques were applied to maintain a relative low power consumption. The circuit was designed with a 0.5 μm CMOS technology. The simulations done with SPICE show a cutoff frequency as high as 2.94 GHz at 3.3 V supply voltage

Keywords

CMOS digital integrated circuits; SPICE; circuit simulation; convolution; digital signal processing chips; high-speed integrated circuits; low-power electronics; 0.5 micron; 2.94 GHz; 3.3 V; CMOS; SPICE; bit-level systolic array architecture; cutoff frequency; digital signal processing; dynamic logic style; high-performance convolver; high-speed operation; low power consumption; low-power techniques; true single-phase clock; unidirectional data flow; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Clocks; Convolution; Convolvers; Digital signal processing; Energy consumption; Signal design; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on

Conference_Location

Puerto Vallarta

Print_ISBN

0-7803-5588-1

Type

conf

DOI

10.1109/MMICA.1999.833621

Filename

833621