An IBM second generation RISC processor architecture

A second-generation RISC (reduced-instruction-set computer) architecture designed to support superscalar implementations which can execute multiple instructions every cycle is described. The architecture provides compound function instructions which allow application path lengths to be less than would be required on many complex-instruction-set computers. This second-generation RISC architecture also exploits advances in optimizing compiler and operating system technology. An extension to the original 801 minicomputer virtual memory architecture for hardware support of database storage is described