DocumentCode
1857572
Title
Targeting Leakage Constraints during ATPG
Author
Fey, Görschwin ; Komatsu, Satoshi ; Furukawa, Yasuo ; Fujita, Masahiro
Author_Institution
VLSI Design & Educ. Center, Univ. of Tokyo, Tokyo
fYear
2008
fDate
24-27 Nov. 2008
Firstpage
225
Lastpage
230
Abstract
In previous technology generations IDDQ testing used to be a powerful technique to detect physical faults that are not covered by standard fault models or functional tests. Due to shrinking feature sizes and consequently increasing leakage currents IDDQ testing becomes difficult in the deep-sub-micron area. One of the problems is the vector dependency of leakage current. Even in good devices the leakage current may vary significantly from one test vector to the next. In this work we present an ATPG framework that allows to generate test vectors within tight constraints on leakage currents. The target range for the leakage current is automatically determined. Experiments on the ITC99 benchmark suite yield test sets that achieve 100% fault coverage for the larger circuits, even when the range is narrowed down to 50% of the standard deviation of random vectors.
Keywords
automatic test pattern generation; benchmark testing; fault simulation; integrated circuit testing; leakage currents; ATPG framework; IDDQ testing; ITC99 benchmark testing; automatic test pattern generation; fault coverage; fault detection; leakage currents; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Current measurement; Fault diagnosis; Fluctuations; Leakage current; Semiconductor device measurement; Sorting; ATPG; IDDQ; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2008. ATS '08. 17th
Conference_Location
Sapporo
ISSN
1081-7735
Print_ISBN
978-0-7695-3396-4
Type
conf
DOI
10.1109/ATS.2008.14
Filename
4711588
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