• DocumentCode
    1857636
  • Title

    Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques

  • Author

    Hsu, Chun-Kai ; Denq, Li-Ming ; Wang, Mao-Yin ; Liou, Jing-Jia ; Huang, Chih-Tsun ; Wu, Cheng-Wen

  • Author_Institution
    Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu
  • fYear
    2008
  • fDate
    24-27 Nov. 2008
  • Firstpage
    245
  • Lastpage
    250
  • Abstract
    With continuing trends to embed more on-chip test circuits, increasing complexity requires more efforts on design and validation. In this paper, we use a wireless test system as an example, to demonstrate the efficiency of system-level techniques in assisting circuit specification exploration, with the goal of area and test-cost reduction. In our experiments, 30% to 50% total costs are saved compared to an initial ad-hoc setup.
  • Keywords
    built-in self test; logic CAD; logic testing; SystemC models; chip-area reduction; logic BIST testing; on-chip wireless test channels; system-level design techniques; test-cost reduction; Automatic testing; Baseband; Circuit simulation; Circuit testing; Costs; Design for testability; Performance evaluation; System testing; System-level design; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Test Symposium, 2008. ATS '08. 17th
  • Conference_Location
    Sapporo
  • ISSN
    1081-7735
  • Print_ISBN
    978-0-7695-3396-4
  • Type

    conf

  • DOI
    10.1109/ATS.2008.19
  • Filename
    4711591
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1857636