Area and Test Cost Reduction for On-Chip Wireless Test Channels with System-Level Design Techniques

With continuing trends to embed more on-chip test circuits, increasing complexity requires more efforts on design and validation. In this paper, we use a wireless test system as an example, to demonstrate the efficiency of system-level techniques in assisting circuit specification exploration, with the goal of area and test-cost reduction. In our experiments, 30% to 50% total costs are saved compared to an initial ad-hoc setup.