SC implementation of FIR filters for digital communication systems

Author

Rocha-Pérez, J. Miguel ; Silva-Martínez, Jose

Author_Institution

Nat. Inst. of Astrophys., Opt. & Electron., Puebla, Mexico

fYear

1999

fDate

1999

Firstpage

179

Lastpage

182

Abstract

In this paper a Switched-Capacitor (SC) architecture for the processing of binary input signals is presented. The architecture is especially useful for the realization of Finite Impulse Response (FIR) filters. A 23-th order Raised-Cosine (RC) filter employing 11 capacitors is designed. The filter has been simulated using a 0.8 μm analog CMOS process. Hspice results have shown the feasibility of the proposed design technique

Keywords

CMOS integrated circuits; FIR filters; digital communication; digital filters; interference suppression; intersymbol interference; mixed analogue-digital integrated circuits; shift registers; switched capacitor filters; 0.8 micron; FIR filters; ISI reduction; SC architecture; SC implementation; analog CMOS process; binary input signals; design technique; digital communication system application; digital control section; digital delays; finite impulse response filters; raised-cosine filter; switched-capacitor architecture; Capacitors; Delay; Digital communication; Digital filters; Equations; Finite impulse response filter; Information filtering; Information filters; Optical filters; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Design of Mixed-Mode Integrated Circuits and Applications, 1999. Third International Workshop on

Conference_Location

Puerto Vallarta

Print_ISBN

0-7803-5588-1

Type

conf

DOI

10.1109/MMICA.1999.833629

Filename

833629