DocumentCode
1857756
Title
USB2.0 Logic Built In Self Test Methodology
Author
Kean Hong Boey ; Wai Mun Ng ; Kok Sing Yap
Author_Institution
Embedded Commun. Group, Intel Microelectron., Penang
fYear
2008
fDate
24-27 Nov. 2008
Firstpage
266
Lastpage
266
Abstract
At-speed testing methodology of the USB2.0 functionality cannot be readily achieved, even with high cost testers. This paper presents a methodology to test USB2.0 at-speed, single port and full functional with a low cost tester.
Keywords
built-in self test; logic testing; system-on-chip; SOC implementation; USB2.0 functionality; logic built-in self-test methodology; single port testing; Automatic testing; Bandwidth; Built-in self-test; Cost function; Design for testability; Logic testing; Microelectronics; Protocols; Rendering (computer graphics); Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2008. ATS '08. 17th
Conference_Location
Sapporo
ISSN
1081-7735
Print_ISBN
978-0-7695-3396-4
Type
conf
DOI
10.1109/ATS.2008.84
Filename
4711597
Link To Document