• DocumentCode
    1857768
  • Title

    Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes

  • Author

    Sasaki, Tomonori ; Nakamura, Yoshiyuki ; Asaka, Toshiharu

  • fYear
    2008
  • fDate
    24-27 Nov. 2008
  • Firstpage
    267
  • Lastpage
    267
  • Abstract
    We showed the new test sequence to solve the at-speed test escapes of SRAM boundary addresses when shared BIST tests the SRAMs of different address sizes in parallel. This test sequence accesses only an address boundary continuously. By using our method, shared BIST can test the SRAMs at-speed in parallel with slight extra area overhead and test time.
  • Keywords
    SRAM chips; built-in self test; logic testing; system-on-chip; SRAM; SoC; address boundary test; shared BIST test; test sequence; Built-in self-test; Circuit testing; Decoding; Design engineering; Electronic equipment testing; Hardware; National electric code; Performance evaluation; Random access memory; BIST; BIST sharing; Parallel test; SRAM; at-speed;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Test Symposium, 2008. ATS '08. 17th
  • Conference_Location
    Sapporo
  • ISSN
    1081-7735
  • Print_ISBN
    978-0-7695-3396-4
  • Type

    conf

  • DOI
    10.1109/ATS.2008.31
  • Filename
    4711598
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1857768