Title :
Shared At-Speed BIST for Parallel Test of SRAMs with Different Address Sizes
Author :
Sasaki, Tomonori ; Nakamura, Yoshiyuki ; Asaka, Toshiharu
Abstract :
We showed the new test sequence to solve the at-speed test escapes of SRAM boundary addresses when shared BIST tests the SRAMs of different address sizes in parallel. This test sequence accesses only an address boundary continuously. By using our method, shared BIST can test the SRAMs at-speed in parallel with slight extra area overhead and test time.
Keywords :
SRAM chips; built-in self test; logic testing; system-on-chip; SRAM; SoC; address boundary test; shared BIST test; test sequence; Built-in self-test; Circuit testing; Decoding; Design engineering; Electronic equipment testing; Hardware; National electric code; Performance evaluation; Random access memory; BIST; BIST sharing; Parallel test; SRAM; at-speed;
Conference_Titel :
Asian Test Symposium, 2008. ATS '08. 17th
Conference_Location :
Sapporo
Print_ISBN :
978-0-7695-3396-4
DOI :
10.1109/ATS.2008.31
