DocumentCode
1857833
Title
DFT Technique to Conclusively Translate Floating Nodes to High IDDQ Current in Analog Circuits
Author
Smith, Ricky ; Shi, Jiang
Author_Institution
Texas Instrum., Houston, TX
fYear
2008
fDate
24-27 Nov. 2008
Firstpage
270
Lastpage
270
Abstract
An IDDQ test sets all CMOS devices into a static digital state and then measures the tiny current leaking from power to ground. For this test to be useful, it is important to be able to conclusively verify IDDQ levels for individual design blocks via a simulation tool. This new methodology can help to conclusively verify that no floating nodes exist in a circuit which could hamper the usefulness of the system´s IDDQ reliability test.
Keywords
CMOS analogue integrated circuits; design for testability; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; leakage currents; CMOS devices; DFT technique; IDDQ test; analog circuits; floating nodes; reliability test; static digital state; Analog circuits; Circuit simulation; Circuit testing; Gravity; Impedance; Resistors; Semiconductor device modeling; System testing; Variable structure systems; Voltage; DFT; Floating node; IDDQ;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Test Symposium, 2008. ATS '08. 17th
Conference_Location
Sapporo
ISSN
1081-7735
Print_ISBN
978-0-7695-3396-4
Type
conf
DOI
10.1109/ATS.2008.70
Filename
4711601
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