• DocumentCode
    1857900
  • Title

    Image processing using a universal nonlinear cell

  • Author

    Jain, V.K. ; Lin, L.

  • Author_Institution
    Dept. of Electr. Eng., Univ. of South Florida, Tampa, FL, USA
  • fYear
    1994
  • fDate
    19-21 Jan 1994
  • Firstpage
    40
  • Lastpage
    51
  • Abstract
    Silicon implementation of many image processing algorithms has been hindered in the past due to their complexity and computational volume. This paper discusses two such algorithms, namely the `Detection of line segments via Hough transform´ and `Backprojection in CT image reconstruction´. To gain a significant speed advantage, we present a multi-function cell for performing one of four nonlinear operations: (1) square-root, (2) reciprocal, (3) sine/cosine, and (4) arctangent-all realized in a single chip, available on a selectable basis, and outputting a new result every two clock cycles. The design and test results of a 24 bit and a 16 bit four-function “two cycle” VLSI chip, both fabricated in 2.0 micron CMOS technology, are described. Also discussed is a new “one-cycle” architecture, which can potentially double the throughput of the chip. Using this nonlinear cell an application level Hough transform module is developed. The Hough module can deliver parameters of the line in the image plane every clock cycle
  • Keywords
    CMOS integrated circuits; Hough transforms; VLSI; computerised tomography; digital signal processing chips; image processing equipment; image reconstruction; image segmentation; 2 mum; CMOS technology; CT image reconstruction; Hough transform; arctangent; backprojection; chip throughput; four-function two cycle VLSI chip; image processing algorithms; line segment detection; multi-function cell; nonlinear function generation; one-cycle architecture; radon transform; reciprocal; sine/cosine; square-root; universal nonlinear cell; CMOS technology; Clocks; Computed tomography; Image processing; Image reconstruction; Image segmentation; Performance gain; Silicon; Testing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-1850-1
  • Type

    conf

  • DOI
    10.1109/ICWSI.1994.291234
  • Filename
    291234