DocumentCode :
1857919
Title :
Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip
Author :
He, Zhiyuan ; Peng, Zebo ; Eles, Petru
Author_Institution :
Embedded Syst. Lab. (ESLAB), Linkoping Univ., Linkoping
fYear :
2008
fDate :
24-27 Nov. 2008
Firstpage :
283
Lastpage :
288
Abstract :
Thermal safety has become a major challenge to the testing of systems-on-chip with deep sub-micron technologies. In order to avoid overheating the devices under test while reducing test application times, new techniques are needed. In this paper, we propose a test scheduling technique to minimize the test application time such that the temperatures of individual cores are kept below a given limit. The proposed approach takes into account thermal influences between cores, and thus accurate temperature evolution information of all cores in a system-on-chip is needed for the test scheduling. In order to avoid overheating, we have employed a thermal simulation driven scheduling algorithm, in which instantaneous thermal simulation results are used to guide the partitioning of test sets into test sub-sequences and to determine cooling periods inserted between the partitions. Furthermore, the partitioned test sets for different cores are interleaved such that a cooling period reserved for one core can be utilized for the test-data transportations and test applications for other cores. Experimental results have shown that by using the proposed technique, the test application time is minimized and the temperatures of cores under test are kept below the temperature limit during the entire test process.
Keywords :
cooling; integrated circuit testing; scheduling; system-in-package; thermal management (packaging); cooling periods; instantaneous thermal simulation; partitioned test sets; simulation-driven thermal-safe test time minimization; system-on-chip; test scheduling technique; thermal safety; thermal simulation driven scheduling algorithm; Circuit testing; Cooling; Costs; Energy consumption; Helium; Interleaved codes; Minimization; System testing; System-on-a-chip; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Asian Test Symposium, 2008. ATS '08. 17th
Conference_Location :
Sapporo
ISSN :
1081-7735
Print_ISBN :
978-0-7695-3396-4
Type :
conf
DOI :
10.1109/ATS.2008.79
Filename :
4711606
Link To Document :
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