High performance low temperature activated devices and optimization guidelines for 3D VLSI integration of FD, TriGate, FinFET on insulator

Author

Pasini, L. ; Batude, P. ; Casse, M. ; Mathieu, B. ; Sklenard, B. ; Luce, F. Piegas ; Reboh, S. ; Bernier, N. ; Tabone, C. ; Rozeau, O. ; Martini, S. ; Fenouillet-Beranger, C. ; Brunet, L. ; Audoit, G. ; Lafond, D. ; Aussenac, F. ; Allain, F. ; Romano, G.

Author_Institution

Leti, CEA, France

fYear

2015

fDate

16-18 June 2015

Abstract

3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.

Keywords

CMOS integrated circuits; MOSFET; circuit optimisation; epitaxial growth; integrated circuit design; three-dimensional integrated circuits; 3D VLSI integration; CMOS scalability; FDSOI devices; FinFET-on-insulator; high performance activated device; low temperature activated device; low temperature processing; optimization guidelines; solid phase epitaxy; trigate field effect transistor; Epitaxial growth; FinFETs; Implants; Junctions; Performance evaluation; Strain; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI Technology), 2015 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2015.7223699

Filename

7223699