• DocumentCode
    1858156
  • Title

    Two-Gear Low-Power Scan Test

  • Author

    Tzeng, Chao-Wen ; Huang, Shi-Yu

  • Author_Institution
    EE Dept, Nat. Tsing-Hua Univ.
  • fYear
    2008
  • fDate
    24-27 Nov. 2008
  • Firstpage
    337
  • Lastpage
    342
  • Abstract
    We introduce in this paper a new scan test methodology that can be programmed to execute in one of two gears - that is, the low-shifting-power scan, and the low-capture-power scan, in one single scan-architecture. This two-gear method provides layered treatment to potential power-induced test failure. First, it attempts to perform scan test in gear 1 without any test time overhead over the traditional scan. Second, in case the failure is caused by excessive capture power, then the test yield loss could be recovered by switching the operation to gear 2, which is a low-capture-power mode, at the cost of extra test time. This methodology is fully compatible with existing DFT tool and requires only small area overhead.
  • Keywords
    design for testability; integrated circuit testing; DFT tool; layered treatment; potential power-induced test failure; two-gear low-power scan test; Chaos; Clocks; Continuous wavelet transforms; Costs; Design for disassembly; Energy consumption; Gears; Logic testing; Performance evaluation; Reduced instruction set computing; Low-Power Scan; Low-capture-power Scan; Multi-Gear Scan; Multi-Testing; Scan Test;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Asian Test Symposium, 2008. ATS '08. 17th
  • Conference_Location
    Sapporo
  • ISSN
    1081-7735
  • Print_ISBN
    978-0-7695-3396-4
  • Type

    conf

  • DOI
    10.1109/ATS.2008.54
  • Filename
    4711614