An architectural approach for increasing clock frequency and communication speed in monolithic-WSI systems

Based on special pipelining techniques, a new methodology for increasing the clock frequency and communication speed in monolithic-WSI systems is proposed. Spice simulations show that the clock frequency on wafer scale systems implemented using a 1.2 micron CMOS technology can be operated well above 140 MHz, which is approximatively five times the maximum frequency of current systems. It is also shown that pipelining principles can be applied to communication links. That particular strategy allows to speedup communication transfers on 5 cm interconnection wires, such as those running across a wafer, by a factor between two and ten, as compared to the case in which no pipelining is used