First experimental demonstration of Ge 3D FinFET CMOS circuits

We report the first experimental demonstration of Ge 3D CMOS circuits, based on the recessed fin structure. Both n-FinFETs and p-FinFETs with channel length (L_ch) from 200 to 20 nm and fin width (W_Fin) from 60 to 10 nm are realized on a Ge-on-insulator (GeOI) substrate. The Ge FinFETs show superior gate electrostatic control over planar devices and sub-threshold slope (SS) as low as 93 and 73 mV/dec are obtained on n- and p-FETs, respectively. Combining the n- and p- type 3D devices together, the FinFET CMOS inverters have high voltage gain up to 34 V/V at V_DD of 1.4 V, delivering more than 200% improvement over the planar ones at the same L_ch of 200 nm. Scalability studies are also carried out for both types of FinFETs in terms of L_ch and W_Fin.