DocumentCode
1858207
Title
Clock synchronization for WSI systems
Author
Embabi, S.H.K. ; Brueske, D.E.
Author_Institution
Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA
fYear
1994
fDate
19-21 Jan 1994
Firstpage
228
Lastpage
234
Abstract
This paper presents a clock synchronisation method which can be used to reduce the clock skew time in WSI systems. A feedback technique is used to offset the clock skewing due to process mismatches and environmental variations. Experiments and simulations indicate that the skew time can be reduced to within a few tens of picoseconds. The stability analysis shows that the system is stable under certain conditions which can be easily satisfied
Keywords
VLSI; clocks; frequency stability; microprocessor chips; parallel architectures; synchronisation; WSI systems; clock skew time; clock synchronisation method; environmental variations; feedback technique; process mismatches; stability analysis; Charge pumps; Circuits; Clocks; Delay; Detectors; Neural networks; Phase detection; Signal processing; Stability analysis; Synchronization;
fLanguage
English
Publisher
ieee
Conference_Titel
Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
Conference_Location
San Francisco, CA
Print_ISBN
0-7803-1850-1
Type
conf
DOI
10.1109/ICWSI.1994.291249
Filename
291249
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