2.8-GB/s-write and 670-MB/s-erase operations of a 3D vertical chain-cell-type phase-change-memory array

Author

Kurotsuchi, K. ; Sasago, Y. ; Yoshitake, H. ; Minemura, H. ; Anzai, Y. ; Fujisaki, Y. ; Takahama, T. ; Takahashi, T. ; Mine, T. ; Shima, A. ; Fujisaki, K. ; Kobayashi, T.

Author_Institution

Central Res. Lab., Hitachi, Ltd., Kokubunji, Japan

fYear

2015

fDate

16-18 June 2015

Abstract

A high-programming-throughput three-dimensional (3D) vertical chain-cell-type phase-change memory (VCCPCM) array for a next-generation storage device was fabricated. To increase the number of write cells at one time by reducing resistance of bit and source lines, the VCCPCM array includes plate electrodes and double-gate vertical-chain-selection MOSs with 5-nm-thick poly-Si channels. In addition, CO₂ laser annealing enhances the drivability of a poly-Si cell MOS to 680 μA/μm to suppress energy loss in the cell MOS. In addition to write throughput, erase throughput is increased by erasing memory cells in a “bundle” by channel heating (called “bundle erase”). GeSbTe CVD with high uniformity is also developed.

Keywords

MOS memory circuits; antimony alloys; carbon compounds; chemical vapour deposition; electrodes; germanium alloys; laser beam annealing; phase change memories; silicon; tellurium alloys; three-dimensional integrated circuits; 3D vertical chain-cell-type phase-change-memory array; CO₂; CVD; GeSbTe; Si; VCCPCM array; bundle erase; cell MOS; channel heating; chemical vapour deposition; double-gate vertical-chain-selection MOS; energy loss; erase throughput; laser annealing; memory cells; next-generation storage device; plate electrodes; write cells; write throughput; Arrays; Electrodes; Logic gates; Microprocessors; Resistance; Throughput;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSI Technology), 2015 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Type

conf

DOI

10.1109/VLSIT.2015.7223705

Filename

7223705