DocumentCode
1858331
Title
A 50-nm 1.2-V Gex Te1−x /Sb2 Te3 superlattice topological-switching random-access memory (TRAM)
Author
Tai, M. ; Ohyanagi, T. ; Kinoshita, M. ; Morikawa, T. ; Akita, K. ; Takato, M. ; Shirakawa, H. ; Araidai, M. ; Shiraishi, K. ; Takaura, N.
Author_Institution
Low-power Electron. Assoc. & Project, Tsukuba, Japan
fYear
2015
fDate
16-18 June 2015
Abstract
A 50nm topological-switching random-access memory (TRAM) was fabricated for the first time. A high-quality GexTe1-x/Sb2Te3 superlattice film enabled set and reset voltages of TRAM to be less than 40% of those of PRAM. Statistical analysis of 16kb data showed the reset voltage to be less than 1.2 V, the lowest as a TRAM test chip.
Keywords
antimony alloys; germanium alloys; integrated circuit testing; logic testing; network topology; random-access storage; statistical analysis; superlattices; tellurium alloys; GexTe1-x-Sb2Te3; PRAM; TRAM test chip; parameter random access memory; reset voltages; size 50 nm; statistical analysis; superlattice film; superlattice topological-switching random-access memory; voltage 1.2 V; Films; Memory management; Metals; Phase change random access memory; Resistance; Superlattices; Voltage measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSI Technology), 2015 Symposium on
Conference_Location
Kyoto
ISSN
0743-1562
Type
conf
DOI
10.1109/VLSIT.2015.7223707
Filename
7223707
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