• DocumentCode
    1858334
  • Title

    An effective framework for fault-tolerant VLSI/WSI arrays based on hybrid redundancy approach

  • Author

    Chen, Yung-Yuan ; Shyu, Yung-Shiuan ; Cheng, Ching-Hwa

  • Author_Institution
    Dept. of Comput. Sci., Chung-Hua Polytech. Inst., Hsinchu, Taiwan
  • fYear
    1994
  • fDate
    19-21 Jan 1994
  • Firstpage
    153
  • Lastpage
    162
  • Abstract
    Proposes a formal hybrid redundancy approach based on the concepts as follows: block partitioning, local reconfiguration and spare sharing, and spare borrowing from upper, lower, and right corresponding blocks. This systematic approach combined the concepts indicated and allows reconfiguration schemes of varying complexity and performance to develop. Two reconfiguration algorithms within such a framework are presented. The authors then develop the switching interconnection networks to support the reconfiguration algorithms proposed. The Markov model combined with the combinatorial model is used to analyze the system yield, and then the Monte Carlo simulation is conducted to justify the theoretical analysis. Finally, they perform the comparisons among the algorithms proposed with other representative algorithms to validate the schemes. The significance of this research is to propose a new framework which can be used to derive a suitable and effective redundancy scheme for a specific application and requirements
  • Keywords
    Markov processes; Monte Carlo methods; VLSI; fault tolerant computing; microprocessor chips; parallel architectures; redundancy; Markov model; Monte Carlo simulation; block partitioning; combinatorial model; fault-tolerant VLSI/WSI arrays; hybrid redundancy approach; local reconfiguration; reconfiguration schemes; spare borrowing; spare sharing; switching interconnection networks; system yield; Algorithm design and analysis; Analytical models; Computer science; Fault tolerance; Fault tolerant systems; Manufacturing; Multiprocessor interconnection networks; Partitioning algorithms; Redundancy; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-1850-1
  • Type

    conf

  • DOI
    10.1109/ICWSI.1994.291256
  • Filename
    291256