Reconfigurable fault tolerant binary tree-implementation in two-dimensional arrays and reliability analysis

We propose a reconfiguration scheme of repairing faulty processors where processors on each level of a binary tree are considered to be a linear array In which spare processors are inserted at regular intervals. The switching networks for compensation are regular and comparatively simple. The logic circuits are simple and their switchings for repair are done autonomously. We give a method of embedding the proposed tree architectures into two-dimensional arrays for WSI implementations. The method embeds the PE´s from the root to a certain level L₀ into a rectangular array, which is called a root module. For levels L(>L₀), the linear array on each level is partitioned into subarrays. Such subarrays are called level modules. A binary tree-connected computer with a specified height is constructed by embedding these modules into two-dimensional arrays. Next, for the proposed scheme. We derive the necessary and sufficient condition for reconfigurability. Using the result, we obtain a formula for computing system´s reliability. The reliabilities of our systems are compared with those of several systems already known, and the effectiveness of our systems is shown