• DocumentCode
    1858394
  • Title

    What designers of wafer scale systems should know about local sparing

  • Author

    LaForge, Laurence E.

  • Author_Institution
    Dept. of Electr. Eng., Nevada Univ., Reno, NV, USA
  • fYear
    1994
  • fDate
    19-21 Jan 1994
  • Firstpage
    106
  • Lastpage
    131
  • Abstract
    Local sparing is a simple way to organize the redundancy of a fault tolerant system. Any system can be locally spared. Furthermore, local sparing preserves both regularity and planarity. In spite of this, the potential usefulness of local sparing appears to have been overlooked. Suppose that the designer wishes to assure, with high probability, a fault-free copy of the n-element system desired. If local sparing is used then, as proved, i) the resulting area is Θ(log n) times the area of the system desired; ii) the wire length is 𝒪(√(log n)) times the maximum wirelength in the desired system; iii) an optimal diagnosis algorithm identifies the faulty elements in Θ(n log2 n) time; iv) in optimal time Θ(n log n+number of wires in the desired system), a simple configuration algorithm achieves a fault-free copy of the desired system if and only if a fault-free copy exists. The authors illustrate these results for arrays, binary trees, and hypercubes. In addition, v) if Y denotes the probability of achieving a fault-free copy of the system desired then, using h-fold redundancy, the maximum rate at which elements can fail is ((-ln Y)/n)1h/. Local sparing is simple, widely-applicable, and low-cost. A disadvantage is that, depending on the system desired, the cost may not be optimal. However, there is strong reason to prefer local sparing over global sparing, and in some cases local sparing is better than more popular approaches to configuration
  • Keywords
    VLSI; fault tolerant computing; hypercube networks; parallel architectures; redundancy; binary trees; configuration algorithm; fault-free copy; h-fold redundancy; hypercubes; local sparing; optimal diagnosis algorithm; planarity; probability; redundancy; regularity; wafer scale systems; wire length; Binary trees; Cost function; Fault diagnosis; Fault tolerant systems; Hypercubes; Internet telephony; Redundancy; Switches; Testing; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Wafer Scale Integration, 1994. Proceedings., Sixth Annual IEEE International Conference on
  • Conference_Location
    San Francisco, CA
  • Print_ISBN
    0-7803-1850-1
  • Type

    conf

  • DOI
    10.1109/ICWSI.1994.291259
  • Filename
    291259