Capacitive-SAR ADC input offset reduction by stray capacitance compensation

A 10-bit, 80-kS/s charge-redistribution successive approximation analog-to-digital converter is presented, which incorporates a novel stray capacitance compensation technique that is appropriate for low-power design in order to accomplish input voltage offset reduction. Three different versions of the ADC were fabricated in 0.35 mum, 4M2P standard CMOS process. The compensation mechanism implemented in one of the ADC versions proved its effectiveness by showing an input voltage offset that is circa 60 times smaller than what was measured in the other two uncompensated versions. Also from fabricated samples of the compensated ADC, measured values for INL and DNL are 0.47 LSB and 0.58 LSB, respectively. Operating at 3.3V at the nominal speed, the offset-compensated ADC consumes 122 muW.