Title :
Intertwined scheduling, module selection and allocation in time-and-area constrained synthesis
Author :
Harris, I.G. ; Orailoglu, A.
Author_Institution :
University of California
Keywords :
Clocks; Control system synthesis; Delay; Hardware; High level synthesis; Libraries; Processor scheduling; Resource management; Scheduling algorithm; Time factors;
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
IEEE
Print_ISBN :
0-7803-1281-3
