Signal transition graph constraints for speed-independent circuit synthesis
Author :
Puri, R.
Author_Institution :
University of Calgary
fYear :
1993
fDate :
3-6 May 1993
Firstpage :
1686
Lastpage :
1689
Keywords :
Asynchronous circuits; Circuit synthesis; Combinational circuits; Concurrent computing; Control system synthesis; Encoding; Hazards; Logic gates; Signal synthesis; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
