A quadratic approach for routability driven placement design: Initial insight

To obtain a good layout quality and reliability, placement plays a critical and fundamental role in the physical design of VLSI circuits as an optimization problem. A compact placement may induce unwanted routing issues. In order to reduce parasitic and cross-talk effects during the routing phase, wires are preferred not to pass above the active area of devices. Therefore, it is required to preserve enough routing spaces between devices for successful routing. Effective placement leading to better routing is of paramount importance in deep submicron technologies. In this paper, we will present the design of a novel routability-driven placer to minimize wire length and area considering congestion problem.