Title :
Guidelines for the noise optimization of 0.18 μm CMOS tuned LNAs
Author :
Youssef, Ahmed ; Haslett, Jim
Author_Institution :
Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada
Abstract :
Based on four noise parameters and two-port noise theory, considerations for noise optimization of fully integrated tuned low-noise amplifier (LNA) designs are presented. This paper demonstrates explicit design guidelines for a 0.18 micron CMOS tuned LNA. These guidelines give a useful indication of the design tradeoffs between noise figure, power dissipation and gate overdrive voltage for the LNA designed using this technology.
Keywords :
CMOS integrated circuits; amplifiers; circuit optimisation; integrated circuit design; integrated circuit noise; 0.18 micron; CMOS tuned LNA design; fully integrated tuned low noise amplifier; gate overdrive voltage; noise figure; noise optimization; noise parameters; power dissipation; two port noise theory; CMOS technology; Circuit noise; Design optimization; Energy consumption; Guidelines; Impedance; Integrated circuit noise; MOSFETs; Noise figure; Noise generators;
Conference_Titel :
Circuits and Systems, 2004. MWSCAS '04. The 2004 47th Midwest Symposium on
Print_ISBN :
0-7803-8346-X
DOI :
10.1109/MWSCAS.2004.1354278
