Design and analysis of a 2.4 GHz fully integrated 1.8V power amplifier in TSMC 180nm CMOS RF process for wireless communication

Fully integrated single stage 1.8V power amplifier working at 2.4GHz is designed in TSMC 180nm CMOS RF process. In this paper, cascode topology with inductively degenerated common-source CMOS power amplifier is suggested with improved gain, isolation, better stability and sufficient linearity over the operating range. Though noise figure is not that much relevant for PA design, optimum matching network is designed to minimize the noise figure (NF) and maximize the power gain. The proposed circuit is simulated using Cadence EDA tools (Version IC 6.14). Results showed that PA delivered 14.08dBm output power with 37% power-added efficiency (PAE) at 1.8V. The proposed PA has a linear power gain of 15.91 dB, S11 and S22 is -12.66dB and -9.22dB respectively and it offers better isolation (-22.56dB) between the ports. The circuit consumed 10.69mW power. Finally, PA is laid out using Cadence virtuoso layout out editor and its size is 0.079mm2.