• DocumentCode
    1859385
  • Title

    Simulation of Large-Scale HPC Architectures

  • Author

    Jones, Ian S. ; Engelmann, Christian

  • Author_Institution
    Comput. Sci. & Math. Div., Oak Ridge Nat. Lab., Oak Ridge, TN, USA
  • fYear
    2011
  • fDate
    13-16 Sept. 2011
  • Firstpage
    447
  • Lastpage
    456
  • Abstract
    The Extreme-scale Simulator (xSim) is a recently developed performance investigation toolkit that permits running high-performance computing (HPC) applications in a controlled environment with millions of concurrent execution threads. It allows observing parallel application performance properties in a simulated extreme-scale HPC system to further assist in HPC hardware and application software co-design on the road toward multi-petascale and exascale computing. This paper presents a newly implemented network model for the xSim performance investigation toolkit that is capable of providing simulation support for a variety of HPC network architectures with the appropriate trade-off between simulation scalability and accuracy. The taken approach focuses on a scalable distributed solution with latency and bandwidth restrictions for the simulated network. Different network architectures, such as star, ring, mesh, torus, twisted torus and tree, as well as hierarchical combinations, such as to simulate network-on-chip and network-on-node, are supported. Network traffic congestion modeling is omitted to gain simulation scalability by reducing simulation accuracy.
  • Keywords
    discrete event simulation; multi-threading; Extreme-scale Simulator; HPC network architectures; application software co-design; concurrent execution thread; large-scale HPC architecture; parallel application performance property; parallel discrete event simulation; performance investigation toolkit; xSim performance investigation toolkit; Accuracy; Bandwidth; Computational modeling; Computer architecture; Message systems; Network topology; Topology; Message Passing Interface; hardware/software co-design; high-performance computing; parallel discrete event simulation; performance evaluation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel Processing Workshops (ICPPW), 2011 40th International Conference on
  • Conference_Location
    Taipei City
  • ISSN
    1530-2016
  • Print_ISBN
    978-1-4577-1337-8
  • Electronic_ISBN
    1530-2016
  • Type

    conf

  • DOI
    10.1109/ICPPW.2011.44
  • Filename
    6047251