• DocumentCode
    1859387
  • Title

    A 0.3V, 12nW, 47fJ/conv, fully digital capacitive sensor interface in 0.18µm CMOS

  • Author

    Savaliya, Ankit ; Mishra, Biswajit

  • Author_Institution
    DA-IICT, VLSI & Embedded Res. Lab., Gandhinagar, India
  • fYear
    2015
  • fDate
    8-10 Jan. 2015
  • Firstpage
    1
  • Lastpage
    6
  • Abstract
    This paper presents a fully-digital ultra low power capacitive sensor interface, which directly converts sensor capacitance to its digital value. Capacitive sensor interface is divided into two parts, 1) Capacitance to time converter (CTC) and 2) time to digital converter (TDC). The proposed design demonstrates the working principle of CTC and TDC and its implementation using UMC 0.18 μm CMOS technology. Demonstration of CTC through capacitive controlled oscillator (CCO) is carried out by keeping sensor capacitance in the range of 5pF - 25pF. CCO generates pulse signals according to sensor capacitance and feeds it to the TDC. TDC consists of a delay line, edge combiner and counter and measures pulse width of pulse signals generated from CCO and gives their digital equivalent value in two forms:- fine timing data and coarse timing data. Finally, control logic unit is implemented to control each unit and to reduce power consumption of TDC design. The power consumption of the proposed interface is 12nW, acquisition time 528 μS, peak FOM of 47 fJ/conv with 6.1 ENOB at an operating voltage of 0.3V.
  • Keywords
    CMOS integrated circuits; capacitive sensors; low-power electronics; oscillators; pulse generators; time-digital conversion; CTC; TDC; UMC CMOS technology; capacitance 5 pF to 25 pF; capacitance to time converter; capacitive controlled oscillator; control logic unit; counter; delay line; digital capacitive sensor interface; edge combiner; power 12 nW; pulse signal generation; pulse width measurement; sensor capacitance; size 0.18 mum; time 528 mus; time to digital converter; voltage 0.3 V; Capacitance; IP networks; Registers; Synchronization;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Systems, Architecture, Technology and Applications (VLSI-SATA), 2015 International Conference on
  • Conference_Location
    Bangalore
  • Print_ISBN
    978-1-4799-7925-7
  • Type

    conf

  • DOI
    10.1109/VLSI-SATA.2015.7050485
  • Filename
    7050485