Title :
Timing error tolerance in nanometer ICs
Author :
Valadimas, S. ; Tsiatouhas, Y. ; Arapoyanni, A.
Author_Institution :
Dept. of Inf. & Telecommun., Univ. of Athens, Athens, Greece
Abstract :
Timing error tolerance turns to be an important design parameter in nanometer technology, high speed and high complexity integrated circuits. In this work, we present a low cost, multiple timing error detection and correction technique, which is based on a new Flip-Flop design. The proposed design approach provides timing error tolerance at the small penalty of one clock cycle delay in the circuit operation for each error correction. In addition, it is characterized by very low silicon area requirements compared to previous design schemes in the open literature. The proposed technique has been applied in a 90nm pipeline design of a digital FIR filter and the simulation results validated its efficiency.
Keywords :
CMOS logic circuits; FIR filters; error correction; error detection; flip-flops; integrated circuit design; nanoelectronics; pipeline processing; timing circuits; CMOS integrated circuits; clock cycle delay; digital FIR filter; flip-flop design; low cost multiple timing error detection; low silicon area technology; nanometer IC; pipeline architecture; pipeline design; size 90 nm; timing error correction technique; timing error tolerance; Clocks; Delay; Flip-flops; Latches; Logic gates; Registers; Error detection and correction; Timing error tolerance; Timing errors; Timing failures;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International
Conference_Location :
Corfu
Print_ISBN :
978-1-4244-7724-1
DOI :
10.1109/IOLTS.2010.5560189
