VLSI architecture prototyping of pipelined IIR digital filter

Author

Alam, Mehboob ; Badawy, Wael

Author_Institution

Dept. of Electr. & Comput. Eng., Calgary Univ., Alta., Canada

Volume

2

fYear

2002

fDate

2002

Firstpage

1031

Abstract

The paper presents a technique for VLSI prototyping pipelining IIR digital filters and offers a detail solution to single chip implementation. The proposed implementation scheme uses the GCLA (generalized cluster look ahead) technique with overflow avoidance to add further stability to the filter. The design using direct and pipelined architecture is implemented on Xilinx V50CS144 device of the Vertex family and optimal results for time were achieved.

Keywords

IIR filters; VLSI; digital filters; equiripple filters; low-pass filters; pipeline processing; DSP; GCLA; VLSI architecture prototyping; Vertex family; Xilinx V50CS144 device; digital signal processing; equiripple low pass IIR filter; filter stability; generalized cluster look ahead; overflow avoidance; pipelined IIR digital filter; pipelined architecture; single chip implementation; Computational complexity; Computer architecture; Digital filters; Finite impulse response filter; Hardware; IIR filters; Pipeline processing; Polynomials; Prototypes; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Electrical and Computer Engineering, 2002. IEEE CCECE 2002. Canadian Conference on

ISSN

0840-7789

Print_ISBN

0-7803-7514-9

Type

conf

DOI

10.1109/CCECE.2002.1013086

Filename

1013086