A PFD and Charge Pump switching circuit to optimize the output phase noise of the PLL in 0.13-µm CMOS

This paper presents the design of a novel Phase Frequency Detector (PFD) and Charge Pump (CP) switching circuits for the frequency synthesizer in phase-locked loop (PLL). Our proposed PFD technique can eliminate the effect of missing edge and phase ambiguity problems in conventional PFDs circuit. Also, a novel CP circuit with a special switching scheme has been incorporated to reduce the current mismatch error and charge injection error problem with this new design technique. The design charge pump current mismatch has been checked in 0.13 μm CMOS process and worst case mismatch error is 0.025 μA for a control voltage range from 0.25 V to 1.0 V for a 1.2 volt supply voltage. Phase noise performance of the proposed PFD and CP circuit is about -117.3 dBc/Hz at 1 MHz offset frequency for a load capacitance of 10 fF. Current noise of our PFD and CP circuit has been measured from the transistors level simulation to find the phase noise of the fractional-N PLL, for output frequency of 2.2 GHz with 40 MHz reference signal in CppSim system simulator. Proposed PFD and CP switching circuit´s phase noise performance shows the 17.36 dB improvement compare to the NOR based PFD and 7.4 dB improvement compare to the NAND based PFD topology. Also, the effect of CP current mismatch and dc offset current at any of the current source or sink has been incorporated to check the effect on spur and phase noise of the fractional-N frequency synthesizer. In addition, charge pump current noise and phase noise modelling has been done here to find the output phase noise of the PLL considering the PFD and CP output current noise measured in transistor level in 0.13 μm CMOS.