Title :
Self-checking arithmetic logic unit with duplicated outputs
Author :
Ocheretny, Vitaly
Author_Institution :
Fraunhofer Inst. for Secure Inf. Technol. (SIT), Germany
Abstract :
In this paper we present a new self-checking ALU with duplicated functional outputs. The arithmetic and logic functions as well as their inverses are implemented within a single ALU cell. Two new ALU cells which are intended for different application requirements (e.g. computational speed, hardware overhead and power consumption) are introduced. The hardware overhead for the implementation of the proposed ALU is lower than the hardware overhead required for complete duplication of the ALU. Thereby, the error detection capabilities are almost the same as for the complete duplication.
Keywords :
digital arithmetic; error detection; fault tolerance; logic circuits; arithmetic functions; computational speed; duplicated functional output; error detection; hardware overhead; logic functions; power consumption; self-checking arithmetic logic unit; Adders; Circuit faults; Conferences; Hardware; Information technology; Logic gates; Power demand;
Conference_Titel :
On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International
Conference_Location :
Corfu
Print_ISBN :
978-1-4244-7724-1
DOI :
10.1109/IOLTS.2010.5560204
