Advancing RF test with open FPGAs

The number of wireless devices, diversity of communication standards, and sophistication of modulation schemes are increasing dramatically each year. With each subsequent generation of technology, the cost of testing wireless devices using traditional techniques also has increased. One way to minimize hardware costs and reduce test time is to use virtual or synthetic instruments along with modular I/O; however, a new approach, software-designed instrumentation, not only provides microprocessor software flexibility but an open, user-programmable FPGA for further customization. This approach gives RF test engineers the ability to reduce test times orders of magnitude beyond what was previously possible without custom or standard-specific instrumentation. In this work, we demonstrate how a software-designed RF instrument can include an architecture that facilitates the record-based model of typical virtual or synthetic instruments. We show how this architecture can be extended with simple FPGA modifications to digitally control the device under test (DUT), reducing capital equipment costs by eliminating unnecessary instruments. We achieve a test time reduction of three orders of magnitude in a power leveling algorithm, common in RF power amplifier test. We also show how a software-designed RF instrument can be completely re-architected to implement a real-time RF channel emulator by including complex mathematical fading models on the FPGA. Using this approach, we demonstrate a 2×2 real-time MIMO channel emulator with up to 36 taps per fading filter.