DocumentCode :
1860070
Title :
Design methodology of VLSI with multiple valued logic
Author :
Summerfield, S.
Author_Institution :
University of Warwick
fYear :
1993
fDate :
3-6 May 1993
Firstpage :
1702
Lastpage :
1705
Keywords :
Arithmetic; Circuit synthesis; Design methodology; Digital systems; Iterative algorithms; Logic design; Multivalued logic; Piecewise linear techniques; Signal synthesis; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1993., ISCAS '93, 1993 IEEE International Symposium on
Conference_Location :
IEEE
Print_ISBN :
0-7803-1281-3
Type :
conf
Filename :
692995
Link To Document :
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